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Power-Optimal Simultaneous Buffer Insertion/Sizing and Wire Sizing

Published: 09 November 2003 Publication History

Abstract

This paper studies the problems of minimizing power dissipationof an interconnect wire by simultaneously considering buffer insertion/sizing and wire sizing (BISWS). We consider two cases, namely minimizing power dissipation with optimal delay constraints, and minimizing power dissipation with a given delay penalty.We derive closed form optimal solutions for both cases. Theseclosed form solutions can be used to efficiently estimate the powerdissipation in the early stages of the VLSI designs. We observe thatthe power dissipation can be much different even with the sameoptimal delay.

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  • (2013)Revisiting automated physical synthesis of high-performance clock networksACM Transactions on Design Automation of Electronic Systems10.1145/2442087.244210218:2(1-27)Online publication date: 11-Apr-2013
  • (2007)A Low-Latency and Low-Power Hybrid Insertion Methodology for Global Interconnects in VDSM DesignsProceedings of the First International Symposium on Networks-on-Chip10.1109/NOCS.2007.4(75-82)Online publication date: 7-May-2007
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cover image ACM Conferences
ICCAD '03: Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
November 2003
899 pages
ISBN:1581137621

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IEEE Computer Society

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Published: 09 November 2003

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ICCAD '03 Paper Acceptance Rate 129 of 490 submissions, 26%;
Overall Acceptance Rate 457 of 1,762 submissions, 26%

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View all
  • (2017)A CPS framework based perturbation constrained buffer planning approach in VLSI designJournal of Parallel and Distributed Computing10.1016/j.jpdc.2016.11.013103:C(3-10)Online publication date: 1-May-2017
  • (2013)Revisiting automated physical synthesis of high-performance clock networksACM Transactions on Design Automation of Electronic Systems10.1145/2442087.244210218:2(1-27)Online publication date: 11-Apr-2013
  • (2007)A Low-Latency and Low-Power Hybrid Insertion Methodology for Global Interconnects in VDSM DesignsProceedings of the First International Symposium on Networks-on-Chip10.1109/NOCS.2007.4(75-82)Online publication date: 7-May-2007
  • (2005)A sensitivity analysis of low-power repeater insertionProceedings of the 15th ACM Great Lakes symposium on VLSI10.1145/1057661.1057720(244-247)Online publication date: 17-Apr-2005
  • (2005)An efficient surface-based low-power buffer insertion algorithmProceedings of the 2005 international symposium on Physical design10.1145/1055137.1055155(86-93)Online publication date: 3-Apr-2005
  • (2004)Practical repeater insertion for low powerProceedings of the 41st annual Design Automation Conference10.1145/996566.996576(30-35)Online publication date: 7-Jun-2004

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