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An Algorithmic Approach for Generic Parallel Adders

Published: 09 November 2003 Publication History

Abstract

Binary addition is the most fundamental and frequentlyused operation. A well-designed adder should be fast andsatisfy the application requirements. We propose an algorithmicapproach to generate an irregular parallel-prefix adder, whichhas minimal delay for a given profile of input signals. It cancover different topologies such as ripple-carry, carry-skip andcarry-select adders. Compared with Kogge-Stone and Brent-Kungadders, the results of the proposed approach have thesmallest output delay.

References

[1]
{1} M. Lehman and N. Burla, "Skip Techniques for high-speed carry-propagation in binary arithmetic circuits", IRE Trans. Electron. Comput., pp. 691-698, Dec 1961.
[2]
{2} J. Hennesey and D. A. Patterson, Computer Architecture - A Quantitative Approach. San Mateo, CA: Morgan Kaufmann, 1990. Appendix A.
[3]
{3} R. P. Brent and H. T. Kung, "A regular layout for parallel adder", IEEE Trans. Comput., Vol. C-31, no. 3, pp. 260-264, Mar. 1983.
[4]
{4} P. M. Kogge and H. S. Stone, "A parallel algorithm for the efficient solution of a general class of recurrence equations", IEEE Trans. Comput., Vol. C-22, no. 8, pp. 786-793, Aug. 1973.
[5]
{5} B. Sugla and D. A. Carlson, "Extreme Area-Time Tradeoffs in VLSI", IEEE Trans. Comput., Vol. 39, no. 2, pp. 251-257, Feb. 1990.
[6]
{6} B. Parhami, Computer Arithmetic, New York, Oxford: Oxford University Press, 2000.
[7]
{7} W. C. Yeh and C. W. Jen, "High-Speed Booth Encoded Parallel Multiplier Design", IEEE Trans. Comput., Vol. 49, no. 7, pp. 692-701, Jul. 2000.
[8]
{8} J.P. Fishburn, "A depth-decreasing heuristic for combinational logic; or how to convert a ripple-carry adder into a carry-lookahead adder or anything in-between", 27th ACM/IEEE Design Automation Conference Proceedings, pp. 361-4, 1990.

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cover image ACM Conferences
ICCAD '03: Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
November 2003
899 pages
ISBN:1581137621

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IEEE Computer Society

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Published: 09 November 2003

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ICCAD '03 Paper Acceptance Rate 129 of 490 submissions, 26%;
Overall Acceptance Rate 457 of 1,762 submissions, 26%

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Cited By

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  • (2018)Tree Structures and Algorithms for Physical DesignProceedings of the 2018 International Symposium on Physical Design10.1145/3177540.3177564(120-125)Online publication date: 25-Mar-2018
  • (2017)A slack-based approach to efficiently deploy radix 8 booth multipliersProceedings of the Conference on Design, Automation & Test in Europe10.5555/3130379.3130651(1153-1158)Online publication date: 27-Mar-2017
  • (2016)A Partial Carry-Save On-the-Fly Correction Multispeculative MultiplierIEEE Transactions on Computers10.1109/TC.2016.252962665:11(3251-3264)Online publication date: 1-Nov-2016
  • (2013)Towards optimal performance-area trade-off in adders by synthesis of parallel prefix structuresProceedings of the 50th Annual Design Automation Conference10.1145/2463209.2488793(1-8)Online publication date: 29-May-2013
  • (2010)A high-speed, energy-efficient two-cycle multiply-accumulate (MAC) architecture and Its application to a double-throughput MAC unitIEEE Transactions on Circuits and Systems Part I: Regular Papers10.1109/TCSI.2010.209119157:12(3073-3081)Online publication date: 1-Dec-2010
  • (2008)Parallel prefix algorithms on the multicomputerWSEAS Transactions on Computer Research10.5555/1466874.14668773:4(213-223)Online publication date: 1-Apr-2008
  • (2008)A novel hybrid parallel-prefix adder architecture with efficient timing-area characteristicIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2007.91550716:3(326-331)Online publication date: 1-Mar-2008
  • (2007)Timing optimization by restructuring long combinatorial pathsProceedings of the 2007 IEEE/ACM international conference on Computer-aided design10.5555/1326073.1326184(536-543)Online publication date: 5-Nov-2007
  • (2007)Area minimization algorithm for parallel prefix adders under bitwise delay constraintsProceedings of the 17th ACM Great Lakes symposium on VLSI10.1145/1228784.1228886(435-440)Online publication date: 11-Mar-2007
  • (2007)Timing-Constrained Area Minimization Algorithm for Parallel Prefix AddersIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences10.1093/ietfec/e90-a.12.2770E90-A:12(2770-2777)Online publication date: 1-Dec-2007
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