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ABSTRACT
Increasing communication demands of processor and memory cores in Systems on Chips (SoCs) necessitate the use of Networks on Chip (NoC) to interconnect the cores. An important phase in the design of NoCs is he mapping of cores onto the most suitable opology for a given application. In this paper, we present SUNMAP a tool for automatically selecting he best topology for a given application and producing a mapping of cores onto that topology. SUNMAP explores various design objectives such as minimizing average communication delay, area, power dissipation subject to bandwidth and area constraints. The tool supports different routing functions (dimension ordered, minimum-path, traffic splitting) and uses floorplanning information early in the topology selection process to provide feasible mappings. The network components of the chosen NoC are automatically generated using cycle-accurate SystemC soft macros from X-pipes architecture. SUNMAP automates NoC selection and generation, bridging an important design gap in building NoCs. Several experimental case studies are presented in the paper, which show the rich design space exploration capabilities of SUNMAP.
REFERENCES
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CITED BY 28
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Márcio Kreutz , César A. Marcon , Luigi Carro , Flávio Wagner , Altamiro A. Susin, Design space exploration comparing homogeneous and heterogeneous network-on-chip architectures, Proceedings of the 18th annual symposium on Integrated circuits and system design, September 04-07, 2005, Florianolpolis, Brazil
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Umit Y. Ogras , Radu Marculescu , Hyung Gyu Lee , Naehyuck Chang, Communication architecture optimization: making the shortest path shorter in regular networks-on-chip, Proceedings of the conference on Design, automation and test in Europe: Proceedings, March 06-10, 2006, Munich, Germany
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Srinivasan Murali , David Atienz , Luca Benini , Giovanni De Michel, A multi-path routing strategy with guaranteed in-order packet delivery and fault-tolerance for networks on chip, Proceedings of the 43rd annual conference on Design automation, July 24-28, 2006, San Francisco, CA, USA
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Stergios Stergiou , Federico Angiolini , Salvatore Carta , Luigi Raffo , Davide Bertozzi , Giovanni De Micheli, ×pipes Lite: A Synthesis Oriented Design Library For Networks on Chips, Proceedings of the conference on Design, Automation and Test in Europe, p.1188-1193, March 07-11, 2005
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Srinivasan Murali , Martijn Coenen , Andrei Radulescu , Kees Goossens , Giovanni De Micheli, Mapping and configuration methods for multi-use-case networks on chips, Proceedings of the 2006 conference on Asia South Pacific design automation, January 24-27, 2006, Yokohama, Japan
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Kees Goossens , John Dielissen , Om Prakash Gangwal , Santiago Gonzalez Pestana , Andrei Radulescu , Edwin Rijpkema, A Design Flow for Application-Specific Networks on Chip with Guaranteed Performance to Accelerate SOC Design and Verification, Proceedings of the conference on Design, Automation and Test in Europe, p.1182-1187, March 07-11, 2005
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Srinivasan Murali , Martijn Coenen , Andrei Radulescu , Kees Goossens , Giovanni De Micheli, A methodology for mapping multiple use-cases onto networks on chips, Proceedings of the conference on Design, automation and test in Europe: Proceedings, March 06-10, 2006, Munich, Germany
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Srinivasan Murali , Paolo Meloni , Federico Angiolini , David Atienza , Salvatore Carta , Luca Benini , Giovanni De Micheli , Luigi Raffo, Designing application-specific networks on chips with floorplan information, Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design, November 05-09, 2006, San Jose, California
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Davide Bertozzi , Antoine Jalabert , Srinivasan Murali , Rutuparna Tamhankar , Stergios Stergiou , Luca Benini , Giovanni De Micheli, NoC Synthesis Flow for Customized Domain Specific Multiprocessor Systems-on-Chip, IEEE Transactions on Parallel and Distributed Systems, v.16 n.2, p.113-129, February 2005
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David Atienza , Federico Angiolini , Srinivasan Murali , Antonio Pullini , Luca Benini , Giovanni De Micheli, Invited paper: Network-on-Chip design and synthesis outlook, Integration, the VLSI Journal, v.41 n.3, p.340-359, May, 2008
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