ABSTRACT
Computer manufacturers offer today multicore with multi-threading capabilities and a broad range of number of cores. An important market today for these multicores is in the server domain. Web servers are a class of servers which are widely used to provide access to files and also as front-ends of more complex services.
In this paper the performance of Apache web server is characterized on multicore chips using Specweb2005 as URL request generator. This benchmark provides three workloads in order to characterize different usage environments. We also compare its performance against Surge that simulates a static web page URL request generator.
We find that the L2 data miss rate per instruction is below 1.4%, more than the 60% of the misses are classified as cold or capacity misses and the true sharing misses represent between 12% and 38% of all the misses. We observe that though the data miss rate is small, accesses to main memory represent up to 42% of the execution time. By contrast the true sharing misses that could be up to 38% of all the misses, represent a small fraction of time due to the small latency of cache-to-cache transfers inside the chip.
- A. R. Alameldeen and D. Wood. Ipc considered harmful for multiprocessor workloads. IEEE Micro, 26(4):8--17, 2006. Google ScholarDigital Library
- P. Barford and M. Crovella. Generating representative web workloads for network and server performance evaluation. In Measurement and Modeling of Computer Systems, pages 151--160, 1998. Google ScholarDigital Library
- L. Barroso and et al. Impact of chip-level integration on performance of oltp workloads. In Proc. of HPCA-6, pages 3--14, 2000.Google Scholar
- L. Barroso and et al. Piranha: A scalable architecture based on single-chip multiprocessing. In Proc. of ISCA-27, pages 282--293, 2000. Google ScholarDigital Library
- L. A. Barroso and et al. Memory system characterization of commercial workloads. In Proc. of ISCA-25, pages 3--14, 1998. Google ScholarDigital Library
- H. W. Cain and et al. An architectural evaluation of java tpc-w. In Proc. of HPCA-7, pages 229--240, 2001. Google ScholarDigital Library
- M. Dubois and et al. The detection and elimination of useless misses in multiprocessors. In Proc. of ISCA-20, pages 88--97, 1993. Google ScholarDigital Library
- P. Foglia and et al. A simulation study of memory performance of smp multiprocessors running a tpc-w workload. IEE CDT Sez. E, 151(2)):93--109, 2004.Google Scholar
- http.//httpd.apache.org/.Google Scholar
- http.//www.spec.org/web2005/.Google Scholar
- http.//www.spec.org/web99/.Google Scholar
- http.//www.spec.org/web99ssl/.Google Scholar
- M. Karlsson and et al. Memory system behavior of java-based middleware. In Proc. of HPCA-9, pages 217--228, 2003. Google ScholarDigital Library
- P. Kongetira and et al. Niagara: A 32-way multithreaded sparc processor. IEEE Micro, 25(2)):21--29, 2005. Google ScholarDigital Library
- P. S. Magnusson and et al. Simics: A full system simulation platform. IEEE Computer, 35(2):50--58, 2002. Google ScholarDigital Library
- M. R. Marty and M. D. Hill. Virtual hierarchies to support server consolidation. In Proc. of ISCA-34, 2007. Google ScholarDigital Library
- C. McNairy and R. Bhatia. The montecito processor. In HOT CHIPS 16, 2004.Google Scholar
- J. A. Redstone and et al. An analysis of operating system behavior on a simultaneous multithreaded architecture. In Proc. of ASPLOS-IX, pages 245--256, 2000. Google ScholarDigital Library
- B. Sinharoy and et al. Power5 system microarchitecture. IBM J. of Res. & Dev., 49(4/5):505--521, 2005. Google ScholarDigital Library
- S. Somogyi and et al. Spatial memory streaming. In Proc. of ISCA-33, pages 252--263, 2006. Google ScholarDigital Library
- SPEC. Specweb2005 release 1.10 benchmark design document, 2006.Google Scholar
- SUN. Ultrasparc iv processor architecture overview, 2004.Google Scholar
- J. M. Tendler and et al. Power4 system microarchitecture. IBM J. of Res. & Dev., 46(1):5--25, 2002. Google ScholarDigital Library
- P. Trancoso and et al. The memory performance of dss commercial workloads in shared-memory multiprocessors. In Proc. of HPCA-3, pages 250--260, 1997. Google ScholarDigital Library
- D. Wallin and et al. Vasa: A simulator infrastructure with adjustable fidelity. In Proc. of PDCS-2005, pages 554--563, 2005.Google Scholar
- Characterization of Apache web server with Specweb2005
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