U. Gläser
ABSTRACT
Bridge-type defects play a dominant role in state-of-the-art CMOS technologies. This paper describes a combined functional and overcurrent-based test generation approach for CMOS circuits, which is optionally based on layout information. Comparative results for benchmark circuits are given to demonstrate the feasibility of voltage-based versus IDDQ-based testing.
- 1.F.J. Ferguson and P. J. Larrabee, "Test Pattern Generation for Realistic Bridge Faults in CMOS Circuits", Proc. IEEE Int. Test Conf. 1991, pp. 492-499 Google Scholar
Digital Library
- 2.S. W. Bollinger and S. F. Midkiff, "On Test Generation for IDDQ Testing of Bridging Faults in CMOS Circuits", Proc. IEEE Int. Test Conf. 1991, pp. 598-607 Google ScholarDigital Library
- 3.E. Isern and J. Figueras, "Test Generation with High Coverage for Quiescent Current Test of Bridging Faults in Combinational Circuits", Proc. IEEE Int. Test Conf. 1993, pp. 73-82 Google ScholarDigital Library
- 4.H. T. Vierhaus, W. Meyer, U. Gl~.ser, "CMOS Bridges and Resistive Transistor Faults: IDDQ versus Delay Effects", Proc. IEEE Int. Test Conf. 1993, Baltimore Google ScholarDigital Library
- 5.W. Maly, P. Nigh, "Built-In Current Testing, a Feasibility Study", Proc. IEEE ICCAD'88, pp. 340-343Google Scholar
- 6.U. Gl~.ser, U. H0bner, H. T. Vierhaus, "Mixed Level Hierarchical Test Generation for Transition Faults and Overcurrent Related Defects", Proc. Int. Test Conf. 1992, pp. 21-29 Google ScholarDigital Library
- 7.G. Spiegel, "Optimized Test Cost using Fault Probabilities", Proc. 3rd European Test Conf., ETC 93, Rotterdam, pp. 188-193, 1993Google ScholarCross Ref
- 8.V. Henkel and U. Golze, "RISCE- A Reduced Instruction Set Circuit Extractor for Hierarchical VLSI Layout Verification", Proc. 25th ACM/IEEE Design Autom. Conf, 1988, pp. 465-470 Google ScholarDigital Library
- 9.F. Brglez, H. Fujiwara, "A Neutral List of 10 Combinational Benchmark Circuits and a Target Translator in FORTRAN", Proc. 1985 Int. Symp. Circ. and Systems, pp. 671-674, 1985Google Scholar
Index Terms
- Test generation for bridging faults in CMOS ICs based on current monitoring versus signal propagation
Recommendations
CMOS inverters based positive type second generation current conveyor
A new versatile class AB low-voltage second generation current conveyor based on CMOS inverters operating in transconductance mode is presented in this letter. Against traditional design based on CCII+, the circuit is able to operate at low supply ...
CMOS current steering logic for low-voltage mixed-signal integrated circuits
A quiet logic family-complementary metal-oxide-semiconductor (CMOS) current steering logic (CSL)-has been developed for use in low-voltage mixed-signal integrated circuits. Compared to a CMOS static logic gate with its output range of /spl Delta/V/sub ...
A 1-V Current-Reused Wideband Current-Mirror Mixer in 180-nm CMOS with High IIP2
A wideband current-mirror mixer in a $$0.18\hbox {-}\upmu \hbox {m}$$0.18-μm CMOS process is presented in this paper for multistandard applications. A current-reuse technique is employed in the transconductance stage by utilizing a current bleeding ...
Comments