Managing Mismatches in Voltage Stacking with CoreUnfolding

Abstract

Five percent to 25% of power could be wasted before it is delivered to the computational resources on a die, due to inefficiencies of voltage regulators and resistive loss. The power delivery could benefit if, at the same power, the delivered voltage increases and the current decreases. This article presents CoreUnfolding, a technique that leverages voltage Stacking to improve power delivery efficiency. Our experiments show that about 10% system-wide power can be saved, the voltage regulator area can be reduced by 30%, di/dt improves 49%, and the power pin count is reduced by 40% (≈ 20% reduction in packaging costs), with negligible performance degradation.

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Index Terms

• Hardware

  • Electronic design automation

    • Physical design (EDA)

      • Power grid design

  • Power and energy

    • Energy distribution

      • Power networks

    • Power estimation and optimization

      • Chip-level power issues