ABSTRACT
Innovations and advancements on physical design (PD) in the past half century significantly contribute to the progresses of modern VLSI designs. While ``Moore's Law'' and ``Dennard Scaling'' have become slowing down recently, physical design society encountered a set of challenges and opportunities. This article is presented at the event of the Life Time Achievement Award for Dr. Satoshi Goto by ISPD 2017. Dr. Goto's career in VLSI designs sets an exemplar role model for young engineers. Thus, we use his contributions as a thread to describe our personal view of physical layout from early back-board ordering to recent multi-dimensional placement and the future.
- R. Aitken, G. Yeric, B. Cline, S. Sinha, L. Shifren, I. Iqbal and V. Chandra, "Physical Design and FinFETs", Proc. ISPD, 2014, pp. 65--68. Google ScholarDigital Library
- C. J. Alpert, "The ISPD98 Circuit Benchmark Suite", Proc. ISPD, 1998, pp. 80--85. Google ScholarDigital Library
- C. Alpert, Z. Li, G.-J. Nam, C. N. Sze, N. Viswanathan and S. I. Ward, "Placement: How or Not"?, Proc. ICCAD, 2012, pp. 283--290. Google ScholarDigital Library
- K.J. Antreich, F.M. Johnnes, and F.H. Kirsch, "A New Approach for Solving the Placement Problem using Force Models," IEEE Int. Symp. Circuits and Systems, 1982, pp. 481--486.Google Scholar
- F. Brglez, D. Bryan and K. Kozminski, "Combinational Profiles of Sequential Benchmark Circuits", Proc. ISCAS, 1989, pp. 1929--1934. Google ScholarCross Ref
- I. S. Bustany, D. Chinnery, J. R. Shinnerl and V. Yutsis, "ISPD 2015 Benchmarks with Fence Regions and Routing Blockages for Detailed-Routing-Driven Placement", Proc. ISPD, 2015, pp. 157--164. Google ScholarDigital Library
- T. F. Chan, J. Cong, M. Romesis, J. R. Shinnerl, K. Sze and M. Xie, "mPL6: A Robust Multilevel Mixed-Size Placement Engine", Proc. ISPD, 2005, pp. 227--229. Google ScholarDigital Library
- T.-C. Chen, Z.-W. Jiang, T.-C. Hsu, H.-C. Chen and Y.-W. Chang, "NTUplace3: An Analytical Placer for Large-Scale Mixed-Size Designs with Preplaced Blocks and Density Constraints", Trans. on CAD, 27(7), 2008, pp. 1228--1240. Google ScholarDigital Library
- C.-K. Cheng and E. S. Kuh, "Module Placement Based on Resistive Network Optimization", Trans. on CAD, 3(3), 1984, pp. 218--225. Google ScholarDigital Library
- S. Goto, I. Cederbaum and B. S. Ting, "Suboptimum Solution of the Back-Board Ordering with Channel Capacity Constraint", IEEE Trans. on CAS CAS-24(11), 1977, pp. 645--652. Google ScholarCross Ref
- S. Goto and E. S. Kuh, "An Approach to the Two-Dimensional Placement Problem in Circuit Layout", IEEE Trans. on CAS CAS-25(4), 1978, pp. 208--217. Google ScholarCross Ref
- S. Goto, "A Two-Dimensional Placement Algorithm for the Master Slice LSI Layout Problem", Proc. DAC, 1979, pp. 11--17. Google ScholarCross Ref
- S. Goto, "An Efficient Algorithm for the Two-Dimensional Placement Problem in Electrical Circuit Layout", IEEE Trans. on CAS CAS-28(1), 1981, pp. 12--18. Google ScholarCross Ref
- S. Goto, T. Matsuda, K. Takamizawa, T. Fujita, H. Mizumura, H. Nakamura and F. Kitajima, "LAMBDA, an Integrated Master-Slice LSI CAD System", Integration, the VLSI Journal 1(1), 1983, Elsevier, pp. 53--69.Google ScholarCross Ref
- O. He, S. Dong, J. Bian, S. Goto and C.-K. Cheng, "A Novel Fixed-Outline Floorplanner with Zero Deadspace for Hierarchical Design", Proc. ICCAD, 2008, pp. 16--23.Google Scholar
- T.C. Hu and E.S. Kuh, VLSI Circuit Layout Theory and Design, IEEE Press, 1985.Google Scholar
- O. He, S. Dong, J. Bian, S. Goto and C.-K. Cheng, "Bus Via Reduction Based on Floorplan Revising", Proc. GLSVLSI, 2010, pp. 9--14. Google ScholarDigital Library
- X. He, T. Huang, L. Xiao, H. Tian, G. Cui and E. F. Y. Young, "Ripple: An Effective Routability-Driven Placer by Iterative Cell Movement", Proc. ICCAD, 2011, pp. 74--79. Google ScholarDigital Library
- X. Hong, G. Huang, Y. Cai, J. Gu, S. Dong, C.-K. Cheng and J. Gu, "Corner Block List: An Effective and Efficient Topological Representation of Non-Slicing Floorplan", Proc. ICCAD, 2000, pp. 8--12.Google Scholar
- A. B. Kahng, "A Roadmap and Vision for Physical Design", Proc. ISPD, 2002, pp. 112--117. Google ScholarDigital Library
- A. B. Kahng, M. Luo, G.-J. Nam, S. Nath, D. Z. Pan and G. Robins, "Toward Metrics of Design Automation Research Impact", Proc. ICCAD, 2015, pp. 263--270. Google ScholarCross Ref
- A. B. Kahng, S. Reda and Q. Wang, "APlace: A General Analytic Placement Framework", Proc. ISPD, 2005, pp. 233--235. Google ScholarDigital Library
- M.-C. Kim, J. Hu and N. Viswanathan, "ICCAD-2014 CAD Contest in Incremental Timing-Driven Placement and Benchmark Suite", Proc. ICCAD, 2014, pp. 361--366.Google ScholarDigital Library
- M.-C. Kim, J. Hu, J. Li and N. Viswanathan, "ICCAD-2015 CAD Contest in Incremental Timing-Driven Placement and Benchmark Suite", Proc. ICCAD, 2015, pp. 921--926. Google ScholarCross Ref
- M.-C. Kim, D.-J. Lee and I. L. Markov, "SimPL: An Effective Placement Algorithm", Trans. on CAD, 31(1), 2012, pp. 50--60. Google ScholarDigital Library
- M.-C. Kim, N. Viswanathan, Z. Li and C. Alpert, "ICCAD-2013 CAD contest in Placement Finishing and Benchmark Suite", Proc. ICCAD, 2013, pp. 268--270. Google ScholarCross Ref
- J. M. Kleinhans, G. Sigl, F. M. Johannes and K. J. Antreich, "GORDIAN: VLSI Placement by Quadratic Programming and Slicing Optimization", Trans. on CAD, 10(3), 1991, pp. 356--365. Google ScholarDigital Library
- E. S. Kuh, Quote from a Recommendation Letter, Personal Communication.Google Scholar
- J. Liu, S. Dong, X. Hong and S. Goto, "Floorplanning with Constraint Extraction based on Interconnecting Information Analysis", Proc. ASICON, 2007, pp. 1084--1087.Google Scholar
- J. Lu, P. Chen, C.-C. Chang, L. Sha, D. Huang, C.-C. Teng and C.-K. Cheng, "ePlace: Electrostatics based Placement using Fast Fourier Transform and Nesterov's Method", Trans. on DAES 20(2), 2015, article 17.Google Scholar
- J. Lu, H. Zhang, P. Chen H. Chang, C.-C. Chang, Y.-C. Wong, L. Sha, D. Huang, Y. Luo, C.-C. Teng and C.-K. Cheng, "ePlace-MS: Electrostatics-Based Placement for Mixed-Size Circuits", IEEE Trans. on CAD 34(5), 2015, pp. 685--698. Google ScholarCross Ref
- M. Marek-Sadowska and S. P. Lin, "Timing Driven Placement", Proc. ICCAD, 1989, pp. 94--97. Google ScholarCross Ref
- I. L. Markov, J. Hu and M.-C. Kim, "Progress and Challenges in VLSI Placement Research", Proc. ICCAD, 2012, pp. 275--282. Google ScholarDigital Library
- H. Murata, K. Fujiyoshi, S. Nakatake and Y. Kajitani, "VLSI Module Placement Based on Rectangle-Packing by the Sequence-Pair", Trans. on CAD, 15(12), 1996, pp. 1518--1524. Google ScholarDigital Library
- G.-J. Nam, "ISPD 2006 Placement Contest: Benchmark Suite and Results", Proc. ISPD, 2006, pp. 167. Google ScholarDigital Library
- G.-J. Nam, C. J. Alpert, P. Villarrubia, B. Winter and M. Yildiz, "The ISPD2005 Placement Contest and Benchmark Suite", Proc. ISPD, 2005, pp. 216--220. Google ScholarDigital Library
- R. H. J. M. Otten, "Automatic Floorplan Design", Proc. DAC, 1982, pp. 261--267. Google ScholarCross Ref
- B. T. Preas and W. M. van Cleemput, "Placement Algorithms for Arbitrarily Shaped Blocks", Proc. DAC, 1979, pp. 474--480. Google ScholarCross Ref
- F. Qiao, I. Kang, D. Kane, E. F. Y. Young, C.-K. Cheng and R. Graham, "3D Floorplan Representations: Corner Links and Partial Order", Proc. 3DIC, 2016, to appear.Google ScholarCross Ref
- N. Quinn and M. Breuer, "A Forced Directed Component Placement Procedure for Printed Circuit Boards", IEEE Trans. on CAS, 26(6), 1979, pp. 377--388. Google ScholarCross Ref
- C. Sechen and A. Sangiovanni-Vincentelli, "The TimberWolf Placement and Routing Package", IEEE Journal of SSC, 20(2), 1985, pp. 510--522. Google ScholarCross Ref
- L. Steinberg, "The Backboard Wiring Problem: A Placement Algorithm," SIAM Review 3(1), 1961, pp. 37--50. Google ScholarDigital Library
- J. E. Stevens, "Fast Heuristic Techniques for Placing and Wiring Printed Circuit Boards", Ph. D. dissertation, University of Illinois at Urbana-Champaign, 1972.Google Scholar
- X. Tang and D. F. Wong, "FAST-SP: A Fast Algorithm for Block Placement Based on Sequence Pair", Proc. ASP-DAC, 2001, pp. 521--526. Google ScholarDigital Library
- A. Thierer and A. Castillo, "Projecting the Growth and Economic Impact of the Internet of Things", Technology Policy, Policy Briefing, Mercatus Center at George Mason University, June 15, 2015, https://www.mercatus.org/system/files/IoT-EP-v3.pdf.Google Scholar
- N. Viswanathan, C. J. Alpert, C. N. Sze, Z. Li and Y. Wei, "The DAC 2012 Routability-driven Placement Contest and Benchmark Suite", Proc. DAC, 2012, pp. 774--782. Google ScholarDigital Library
- N. Viswanathan, C. J. Alpert, C. N. Sze, Z. Li and Y. Wei, "ICCAD-2012 CAD Contest in Design Hierarchy Aware Routability-Driven Placement and Benchmark Suite", Proc. ICCAD, 2012, pp. 345--348. Google ScholarDigital Library
- N. Viswanathan, C. J. Alpert, C. N. Sze, Z. Li, G.-J. Nam and J. A. Roy, "The ISPD-2011 Routability-Driven Placement Contest and Benchmark Suite", Proc. ISPD , 2011, pp. 141--146. Google ScholarDigital Library
- N. Viswanathan, M. Pan and C. Chu, "FastPlace 3.0: A Fast Multilevel Quadratic Placement Algorithm with Placement Congestion Control", Proc. ASP-DAC, 2007, pp. 135--140.Google ScholarDigital Library
- M. B. Weindling, "A Method for the Best Geometric Placement of Units on a Plane", Proc. DAC, 1964, pp. 5.1--5.54. Google ScholarDigital Library
- G. J. Wipfler, M. Wiesel and D. A. Mlynski, "A combined force and cut algorithm for hierarchical VLSI layout" Proc. DAC, 1982, pp. 671--677. Google ScholarCross Ref
- D. F. M. Wong and C.-L. Liu "A New Algorithm for Floorplan Design", Proc. DAC, 1986, pp. 101--107. Google ScholarCross Ref
- J. Z. Yan, N. Viswanathan and C. Chu, "Handling Complexities in Modern Large-Scale Mixed-Size Placement", Proc. DAC, 2009, pp. 436--441. Google ScholarDigital Library
- S. Yang, A. Gayasen, C. Mulpuri, S. Reddy and R. Aggarwal, "Routability-Driven FPGA Placement Contest", Proc. ISPD, 2016, pp. 139--143. Google ScholarDigital Library
- V. Yutsis, I. S. Bustany, D. Chinnery, J. Shinnerl and W.-H. Liu, "ISPD 2014 Benchmarks with Sub-45nm Technology Rules for Detailed-Routing-Driven Placement", Proc. ISPD, 2014, pp. 161--168. Google ScholarDigital Library
- ISPD-2017 Contest, http://www.ispd.cc/contests/17/.Google Scholar
- ITRS Report 2015 Edition, http://www.semiconductors.org/main/2015_international_technology_roadmap_for_semiconductors_itrs/.Google Scholar
- Hardware Design Cost: Faster, Cooler, Simpler, could FD-SOI be Cheaper too?, https://www.semiwiki.com/forum/content/2991-faster-cooler-simpler-could-fd-soi-cheaper-too.html.Google Scholar
- Many Ways to Shrink: The Right Moves to 10 Nanometer and Beyond, https://staticwww.asml.com/doclib/investor/asml_3_Investor_Day-Many_ways_to_shrink_MvdBrink1.pdGoogle Scholar
Index Terms
- Physical Layout after Half a Century: From Back-Board Ordering to Multi-Dimensional Placement and Beyond
Recommendations
MP-Trees: A Packing-Based Macro Placement Algorithm for Modern Mixed-Size Designs
In this paper, we present a new multipacking-tree (MP-tree) representation for macro placements to handle modern mixed-size designs with large macros and high chip utilization rates. Based on binary trees, the MP-tree is very efficient, effective, and ...
An Effective Floorplan-Guided Placement Algorithm for Large-Scale Mixed-Size Designs
In this article we propose an effective algorithm flow to handle modern large-scale mixed-size placement, both with and without geometry constraints. The basic idea is to use floorplanning to guide the placement of objects at the global level. The flow ...
Combinatorial techniques for mixed-size placement
While recent literature on circuit layout addresses large-scale standard-cell placement, the authors typically assume that all macros are fixed. Floorplanning techniques are very good at handling macros, but do not scale to hundreds of thousands of ...
Comments