ABSTRACT
Hybrid photonic-electronic networks-on-chip (HPENoCs) harness the strengths of both photonic and electronic links to meet the stringent demands of bandwidth, power, and latency of many-core systems. Microring resonators (MRRs), fundamental components in on-chip photonic networks, are highly sensitive to thermal variations, which may lead to erroneous optical transmission. Previously, we proposed a thermal-aware fault-tolerant routing technique (TAFT) to address this problem. In this paper, we examine and evaluate the scalability of TAFT as the NoC size grows. Organizing the NoC into different size clusters is a crucial part of TAFT scalability. Given the same number of cores, different cluster sizes can have up to 45% latency difference. The latency, throughput and power consumption are all dependent on cluster size, under similar traffic patterns. Simulation results also show that as the traffic pattern degrades, revising cluster size can yield up to 56% latency improvement.
- 2015 International Technology Roadmap for Semiconductors. https://www.semiconductors.org/main/2015_international_technology_roadmap_for_semiconductors_itrs/.Google Scholar
- Mo Yang and Paul Ampadu. Thermal-aware Adaptive Fault-Tolerant Routing for Hybrid Photonic-Electronic NoC. NoCArc'16 Proceedings of the 9th International Workshop on Network on Chip Architectures, pages 33--38, Taiwan, 2016. Google ScholarDigital Library
- S. Bahirat and S. Pasricha. Meteor: hybrid photonic ring- mesh network-on-chip for multicore architectures. ACM Transactions on Embedded Computing Systems (TECS), 13(3s):116, 2014. Google ScholarDigital Library
- Y. Xie, M. Nikdast, J. Xu, W. Zhang, Q. Li, X. Wu, Y. Ye, X. Wang, and W. Liu. Crosstalk noise and bit error rate analysis for optical network-on-chip. Proceedings of the 47th Design Automation Conference, pages 657--660. ACM, 2010. Google ScholarDigital Library
- J. Kim, W. J. Dally, S. Scott, D. Abts. Technology-Driven, Highly-Scalable Dragonfly Topology. 35th International Symposium on Computer Architecture 2008 (ISCA'08), pages 77--88, Beijing, China, 2008.Google ScholarDigital Library
- L. Xiu. Clock Technology: The Next Frontier. IEEE Circuits and Systems Magazine, vol. 17, issue 2, pages 27--46, 2017. Google ScholarCross Ref
- N. Baby, S. Mathew, S. Abraham, S. Ravindranath, Sanju V. Network on Chip Simulator: Design, Implementation and Comparison of Mesh, Torus and RiCoBiT Toppologies. 2016 2nd International Conference on Next Generation Computing Technologies (NGCT-2016), Dehradun, India, 2016.Google ScholarCross Ref
- P. P. Pande, C. Grecu, M. Jones, A. Ivanov, R. Saleh. Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures. IEEE Transactions on Computers, pages 1025--1040, vol. 54, no. 8, August 2005. Google ScholarDigital Library
- B. Grot, J. Hestness, S. W. Keckler, O. Mutlu. Kilo-NOC: A Heterogeneous Network-on-Chip Architecture for Scalability and Service Guarantees. 38th Annual International Symposium on Computer Architecture (ISCA), San Jose, CA, USA, 2011. Google ScholarDigital Library
- M. Yang and P. Ampadu. Energy-efficient power trimming for reliable nanophotonic noc microring resonators. 2016 IEEE International Symposium on Circuits and Systems (ISCAS), pages 1682--1685. IEEE, 2016. Google ScholarDigital Library
- Z. Li, A. Qouneh, M. Joshi, W. Zhang, X. Fu, and T. Li. Aurora: A cross-layer solution for thermally resilient pho- tonic network-on-chip. Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, 23(1):170--183, 2015.Google Scholar
- T. Zhang, J. L. Abell'an, A. Joshi, and A. K. Coskun. Thermal management of manycore systems with silicon-photonic networks. Design, Automation and Test, Europe Conference and Exhibition (DATE), pages 1--6, 2014.Google Scholar
- D. Dang, S. V. R. Chittamuru, R. Mahapatra and S. Pasricha. Islands of heaters: A novel thermal management framework for photonic NoCs, 22nd Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 306--311, Chiba, 2017. Google ScholarDigital Library
- S. Werner, J. Navaridas and M. Luján. Designing Low-Power, Low-Latency Networks-on-Chip by Optimally Combining Electrical and Optical Links, 2017 IEEE International Symposium on High Performance Computer Architecture (HPCA), pp. 265--276, Austin, TX, 2017. Google ScholarCross Ref
- Y. Pan, P. Kumar, J. Kim, G. Memik, Y. Zhang, and A. Choudhary. Firefly: illuminating future network-on-chip with nanophotonics. ACM SIGARCH Computer Architecture News, volume 37, pages 429--440. ACM, 2009. Google ScholarDigital Library
- Nan Jiang, Daniel U. Becker, George Michelogiannakis, James Balfour, Brian Towles, John Kim and William J. Dally. A Detailed and Flexible Cycle-Accurate Network-on-Chip Simulator. In Proceedings of the 2013 IEEE International Symposium on Performance Analysis of Systems and Software, 2013.Google Scholar
Index Terms
- Improving Scalability in Thermally Resilient Hybrid Photonic-Electronic NoCs
Recommendations
Exploring hybrid photonic networks-on-chip foremerging chip multiprocessors
CODES+ISSS '09: Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesisIncreasing application complexity and improvements in process technology have today enabled chip multiprocessors (CMPs) with tens to hundreds of cores on a chip. Networks on Chip (NoCs) have emerged as scalable communication fabrics that can support ...
Photonic NoCs: System-Level Design Exploration
Network-on-chip is a key enabling technology to address the challenges of interconnecting the increasing number of cores in emerging chip multiprocessors. By leveraging recent advances in the CMOS integration of photonic devices and the unique ...
Enhancing Butterfly Fat Tree NoCs for FPGAs with Lightweight Flow Control
FPGA '19: Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate ArraysFPGA overlay networks-on-chip (NoCs) based on Butterfly Fat Tree (BFT) topology and lightweight flow control can outperform state-of-the-art FPGA NoCs, such as Hoplite and others, on metrics such as throughput, latency, cost and power efficiency, and ...
Comments